The disclosure herein relates generally to data processing, and more particularly, to methods, apparatus, and systems for optimizing address translations in a computer system.
Among other tasks, memory management manages the data stored in a computer including overseeing the retrieval and storage of data from memory in a computer. Memory management is often a key factor in overall system performance for a computer. Computer systems often include physical memory used to store applications and data. Modern computers typically rely on a memory management technique known as virtual memory management to increase performance and provide greater flexibility in computers and the underlying architectural designs upon which they are premised.
With a virtual memory system, the underlying hardware implementing the memory system of a computer is effectively hidden from the software of the computer. A relatively large virtual memory space, e.g., 64-bits or more in width, is typically used for such a computer, with computer programs that execute on the computer accessing the memory system using addresses pointing to locations in the virtual memory space. The physical memory devices in the computer, however, are accessed via “real” addresses that map directly into specific memory locations in the physical memory devices. Hardware and/or software in the computer are provided to perform “address translation” to map the real memory addresses of the physical memory to virtualized addresses in the virtual memory space. As such, whenever a computer program on a computer attempts to access memory using a virtualized address, the computer translates the virtualized address into a corresponding real address so that the access can be made to the appropriate location in the appropriate physical device mapped to the virtualized address.
One feature of virtual addressing is that it not necessary for a computer to include storage for the entire virtual memory space in the physical memory devices in the computer's main memory. Instead, lower levels of storage, such as disk drives and other mass storage devices may be used as supplemental storage, with memory addresses grouped into “pages” that are swapped between the main memory and supplemental storage as needed (“paging”). When the processing system uses paging, the low order bits of the virtual address are preserved and used directly as the low order bits of the actual physical address, while the high order bits may be treated as a key or index to one or more address translation tables that correspond to a range of consecutive physical addresses. The memory referenced by such a range may be called a page. Page sizes may range in size, for example, from 512 bytes through 8 megabytes.
In addition, some computer designs also include the concept of segmentation, which partitions the virtual memory into different segments in order to facilitate and simplify the handling of large and growing data structures, and otherwise provide greater flexibility for performing memory management when multiple processes are capable of being handled in a computer at any given time. Each segment typically is mapped to blocks of pages. When segmentation is used, an additional layer of virtualization is used, requiring an additional translation to be performed. Typically, in systems incorporating segmentation and paging, computer programs access the memory system using “effective” addresses, thus requiring a translation first from effective (EA) address to intermediate or virtual address (VA), and then from intermediate or virtual address (VA) to real address (RA).
Address translation in a virtual memory system typically incorporates accessing various address translation data structures. One such structure, referred to as a segment table, includes multiple entries that map effective addresses to intermediate virtual addresses on a segment-by segment basis. Another such structure, referred to as a page table, includes multiple entries that map intermediate virtual addresses to real addresses on a page-by-page basis. Using virtual addressing, processors can access memory using physical addresses that are generated from translating effective addresses (EA) to intermediate or virtual addresses (VA) and translating intermediate or virtual addresses (VA) to physical or real addresses (RA).
Often, due to the large number of memory accesses that constantly occur in a computer, the number of entries required to map all of the memory address space in use by a computer can be significant, and requires the entries to be stored in main storage, rather than in dedicated memory, which makes accessing such entries slow. To accelerate address translation, high speed memories referred to as segment look-aside buffers (SLB) and translation look-aside buffers (TLB) are typically used to cache recently-used entries for quick access by the computer. A SLB is a cache of segment table entries mapping effective addresses (EA) to intermediate or virtual addresses (VA). A TLB is a cache of page table entries mapping intermediate or virtual addresses (VA) to physical addresses or real addresses (RA). With each memory access, the EA is presented to the SLB, which if the SLB hits the SLB provides the VA, and then the VA is presented to the TLB which if the TLB hits the TLB provides a real address (RA) to the processor. If the address misses in the SLB or TLB, a more costly hardware handler or software handler is invoked to load and insert the required segment table entry into the SLB, and/or the page table entry into the TLB so the address will hit in the SLB and TLB and the memory access can proceed.
Due to the frequency of memory access requests in a computer, address translation can have a significant impact on overall system performance. As such, it is desirable to minimize the amount of time to provide an address translation.